In cell-based design, various types of logic cells that are designed in advance and registered as libraries are combined to design an LSI (large-scale integrated) circuit. Logic cells prepared in advance are called standard cells, which may include basic circuit gates and more complex logic circuits such as flip flops. Cells incorporated in cell-based design may also include macro-cells or the like defining larger-scale circuits such as a ROM, a RAM, and an AD converter.
FIG. 1 is a drawing illustrating a standard-cell-placement area used in cell-based design. In a standard-cell-placement area 10, Vdd lines 12 for supplying a power supply potential Vdd and Gnd lines 13 for supplying a ground potential Gnd are arranged alternately at constant intervals. An area between a Vdd line 12 and an adjacent Gnd line 13 constitutes a cell-placement row 11 having a constant height (and width). Each cell-placement row 11 has an N well 14 and a P well 15 formed therein that extend in the same direction as the direction in which the cell-placement row 11 extends. The N well 14 is electrically connected to the corresponding Vdd line 12 through a contact, and the P well 15 is electrically connected to the corresponding Gnd line 13 through a contact.
In an example illustrated in FIG. 1, a standard cell 16 has the same height as the cell-placement row 11, and a standard cell 17 has a height twice as large as the cell-placement row 11. In this manner, the height of a standard cell is restricted to the same height as the cell-placement row 11 or an integer multiple of the height of the cell-placement row 11. This ensures that an orderly cell arrangement is naturally obtained upon placing a plurality of standard cells, thereby simplifying the task of placing cells.
A general standard cell includes one or more P-channel-type transistors (i.e., PMOS transistors) and one or more N-channel-type transistors (i.e., NMOS transistors). PMOS transistors are formed in the N well 14, and NMOS transistors are formed in the P well 15. As was previously described, the N well 14 is connected to the corresponding Vdd line 12. Because of this, it is preferable for the N well 14 to extend along and in parallel to the Vdd line 12 (i.e., in parallel to the cell-placement row 11). Similarly, the P well 15 is connected to the corresponding Gnd line 13. Because of this, it is preferable for the P well 15 to extend along and in parallel to the Gnd line 13 (i.e., in parallel to the cell-placement row 11). Further, with a premise that the N well 14 and the P well 15 are formed in parallel to the cell-placement row 11 as illustrated in FIG. 1, a standard cell that is designed based upon this premise can be placed anywhere in the cell-placement row 11 without modifying the design of the wells. In this manner, a standard cell is typically designed based upon a premise that the N well 14 and the P well 15 are formed in parallel to the cell-placement row 11 as illustrated in FIG. 1.
FIG. 2 is a drawing illustrating a configuration in which a plurality of latches for storing a plurality of bits are arranged in line on the cell-placement row. In FIG. 2, six latches 20, each of which is a standard cell, are arranged in the cell-placement row 11 without having any gaps therebetween. The six latches 20 can store 6 bit data. One of the six latches 20 may store a parity bit that is generated from the 5-bit data stored in the five remaining latches 20. Nine latches 20 may be arranged instead of six latches. Such nine latches can store one-byte data and one parity bit.
As the size of semiconductor elements such as transistors is reduced, a critical charge amount (i.e., the amount of electric charge needed to invert stored data) decreases because of reduction in the power supply voltage and internal capacitance of a memory element such as a latch. This results in an increase in the probability of soft error by which stored data is inverted due to an arrival of α ray or neutron ray. Entry of α ray into an N well or P well, for example, results in a large number of electron-hole pairs being generated in the well. These electron-hole pairs are then scattered in every direction within the well. Electrons generated by an arrival of α ray into an N well tend to be collected by Vdd since the N well is coupled to the power supply potential Vdd. Also, electrons are the majority carrier in the N well. Because of this, these electrons have little effect on P-type diffusion regions existing in the N well. Holes generated together with these electrons, however, end up changing the potential of the P-type diffusion regions existing in the N well upon being collected by these regions. Especially when the P-type diffusion regions are coupled to the ground voltage Gnd, the above-noted change occurs as a change toward higher potentials, thereby causing soft error. Holes generated by an arrival of α ray into a P well tend to be collected by Gnd since the P well is coupled to the ground potential Gnd. Also, holes are the majority carrier in the P well. Because of this, these holes have little effect on N-type diffusion regions existing in the P well. Electrons generated together with these holes, however, end up changing the potential of the N-type diffusion regions existing in the P well upon being collected by these regions. Especially when the N-type diffusion regions are coupled to the ground voltage Gnd, the above-noted change occurs as a change toward lower potentials, thereby causing soft error.
When latches are formed in the common N well 14 and P well 15 as illustrated in FIG. 2, electrons and holes generated by an arrival of α ray into a well are scattered in the well, thereby causing soft error in the plurality of latches in some cases. An error occurring only with respect to one bit among the plurality of bits stored in the latches 20 can be detected by a parity check. Further, the use of a mechanism for correcting error by use of error correction code makes it possible to detect and correct an error in the case of one-bit error. However, errors occurring with respect to two bits among the plurality of bits stored in the latches 20 cannot be correctly detected by a parity check. Further, the mechanism for correcting error by use of error correction code can detect two-bit errors, but cannot correct these errors. Moreover, errors occurring with respect to three or more bits cannot be correctly detected even by use of error correction codes. Occurrence of errors in a plurality of bits may thus result in a performance drop due to a need for an extra action such as an instruction retry, or may result in a failure to perform correct circuit operations.
Measures for preventing soft error may be taken as follows. The number of transistors may be increased and a new latch structure may be devised such as in the case of DICE (i.e., Dual Interlocked Storage Cell), for example, thereby increasing a tolerance level of a latch against soft error. Also, the size of transistors in a latch may be increased to increase the critical charge amount, thereby increasing a tolerance level of the latch against soft error. Moreover, the distance between adjacent latches for storing adjacent bits may be increased to reduce the possibility of electrons reaching the adjacent bit upon being generated by an arrival of α ray. Further, a dummy P-well region (or N-well region) may be provided on a memory-cell border in the common N-type well region (or P-type well region) shared by adjacent memory cells as disclosed in Patent Document 1, thereby reducing soft error.
In cell-based design, however, the above-noted methods of increasing a soft-error tolerance level are faced with problems as follows. Devising a latch structure such as a DICE latch or increasing a critical charge amount by enlarging transistor size give rise to a problem in that power consumption and circuit size significantly increase. Further, an increase in the soft-error tolerance of a latch does not completely remove the possibility of soft error. When error occurs, therefore, plural bits may suffer errors if a common well region is used as in the previously-described cell-based design. An increase in the distance between adjacent latches for storing adjacent bits also gives rise to a problem of a size increase. If the distance is not sufficiently increased due to consideration to the problem of a size increase, the possibility of plural bit errors is not sufficiently lowered.
If the configuration in which a dummy well region is provided between adjacent memory cells as disclosed in Patent Document 1 is applied to the well structure illustrated in FIG. 2, N wells and P wells end up being arranged in a checkerboard pattern. Namely, dummy P-well regions are inserted into the N well 14 between adjacent latches 20 illustrated in FIG. 2, and, also, dummy N-well regions are inserted into the P well 15 between adjacent latches 20, so that the dummy P-well regions and the dummy N-well regions are opposed to each other. Each dummy well region is isolated, and needs to satisfy the minimum size requirement of a well as defined by the process used. This requirement causes the size of a dummy well region to be relatively large. The fact that each well region is isolated also gives rise to a problem in that an area for coupling each well to the corresponding potential may need to be newly provided. Moreover, an actual process involves manufacturing error. Because of this, the same-conduction-type wells may be connected to each other in a diagonal direction at the corners of wells. It may thus be the case that the wells cannot be completely separated from each other between adjacent latches 20.    [Patent Document 1] Japanese Patent Application Publication No. 2002-353413    [Patent Document 2] Japanese Patent Application Publication No. 2010-4019